1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to the improvement of a method of forming a flattened interlayer insulating film on a semiconductor substrate comprising a convexo-concave pattern of an element, a wiring and the like.
2. Description of the Background Art
A semiconductor device technique has already reached a submicron region and a 4MDRAM is about to be implemented by design rule of approximately 0.8 .mu.m. At the same time of miniaturization, the configuration of the device pattern becomes complicated, the difference between step portions becomes considerably large and an aspect ratio becomes higher. Under such a condition, a flattening technique plays an important part at present.
FIGS. 8A to 8I are sectional views of steps of manufacturing a semiconductor device employing a conventional flattening technique.
Referring to FIG. 8A, a semiconductor substrate 1, for example a silicon semiconductor substrate is prepared. Then, referring to FIG. 8B, a silicon oxide film 2 serving as a gate oxide film is formed on the semiconductor substrate 1. A polysilicon layer 3 serving as a gate electrode is formed on the silicon oxide film 2. Then, phosphorus is doped on the polysilicon layer 3 to increase conductivity Instead of doping phosphorus, polysilicon doped with phosphorus or arsenic may be deposited on the silicon oxide film 2.
Referring to FIGS. 8B and 8C, a gate oxide film 4 and a gate electrode 5 are formed on the semiconductor 10 substrate 1 by patterning the silicon oxide film 2 and the polysilicon layer 3 into desired configurations.
Referring to FIG. 8D, in order to form a source-drain region 6 on the main surface of the semiconductor substrate 1, impurity ions 7 of B.sup.+, P.sup.+ or As+ are implanted in the main surface of the semiconductor substrate. The concentration of the impurity ions is approximately 1.about.2.times.10.sup.20 atom/cm.sup.3.
Thereafter, referring to FIG. 8E, an interlayer insulating film 8 formed of a silicon oxide film comprising impurities such as boron, phosphorus, arsenic and the like is deposited on the semiconductor substrate 1 comprising a gate electrode 5. Referring to FIG. 8F, in order to flatten the surface of the interlayer insulating film 8, heat treatment, called reflow, is given at a temperature of approximately 700.degree..about.1000.degree. C. By this reflow treatment, the surface of the interlayer insulating film 8 is flattened.
Referring to FIG. 8G, a resist 9 is applied to the whole surface and patterned such that an opening portion may be formed on an upper portion of a contact region to be formed. Then, a contact hole 10 is formed in the interlayer insulating film 8 by etching the interlayer insulating film 8, using the patterned resist 9 as a mask. Thereafter, the resist 9 is removed.
Then, referring to FIG. 8H, in order to enhance electric conductivity at a contact region 11, impurity ions 12 of B.sup.+, P.sup.+, As.sup.+ and the like are implanted in the contact region 11.
Referring to FIG. 8I a wiring pattern 13 electrically connected to the source/drain region 6 is formed on the interlayer insulating film 8 through the contact hole 10.
The above-described method is the most standard technique of flattening the interlayer insulating film.
However, there is a disadvantages in the technique of flattening the interlayer insulating film that the concentration of impurities implanted in the interlayer insulating film 8 as shown in FIG. 8F is high, and the temperature at the reflow treatment is also high, so that the impurities implanted in the interlayer insulating film 8 are diffused over the gate electrode 5, other wiring layers and the like.
In order to solve this disadvantage, an improved technique for flattening the interlayer insulating film, shown in FIGS. 9A to 9F, is disclosed in Japanese Patent Laying-Open Gazette No. 48140/1988.
Referring to FIG. 9A, a LOCOS oxide film 14, a gate oxide film 4, a gate electrode 5, a source/drain region 6 are formed on the main surface of a semiconductor substrate 1. Referring to FIG. 9B, a silicon oxide film 15a comprising phosphorus of 4.times.10.sup.9 atom/cm.sup.3 is deposited on the whole surface of the semiconductor substrate 1 and a silicon oxide film 15b comprising phosphorus of 1.times.10.sup.10 atom/cm.sup.3 is deposited thereon. Then, a thick insulating film 16 formed of the silicon oxide films 15a and 15b is formed. Thereafter, referring to FIG. 9C, heat treatment, called reflow, is given for 30 minutes in a nitride atmosphere at 1000.degree. C. By this reflow treatment, the surface of the thick insulating film 16 is flattened.
Referring to FIGS. 9C and 9D, by etching the thick insulating film 16 until it becomes a predetermined film thickness, an interlayer insulating film 8 having a predetermined film thickness is formed out of the thick insulating film 16. Thereafter, a portion 17 damaged by the above etching is etched away using acid such as boric acid, phosphoric acid, hydrofluoric acid and the like. Thereafter, referring to FIG. 9E, a resist 9 is applied to the whole surface and then patterned.
Referring to FIGS. 9E and 9F, a contact hole 10 is provided in the interlayer insulating film 8 using the patterned resist 9 as a mask to form a wiring pattern 13.
According to the above-described improved technique, the concentration of impurities implanted in the insulating film 16 can be decreased and the temperature at 10 the reflow treatment can be lowered. However, the reflow treatment is inevitably required in order to flatten the insulating film 16 in the above-described improved technique also. Since the reflow treatment is given at a high temperature of 1000.degree. C., the impurities implanted in the insulating film 16 are somewhat diffused over the wiring layer and the like. Therefore, this improved technique cannot perfectly prevent the impurities implanted in the insulating film 16 from diffusing by heat over the wiring layer and the like. In addition, referring to FIG. 9D, there is a disadvantage in this improved technique that boric acid, phosphoric acid, hydrofluoric acid and the like which were used in etching is soaked in the surface of the interlayer insulating film 8, so that they are left. If acid is left on the surface layer of the interlayer insulating film, the adhesion between the photoresist 9 and the interlayer insulating film 8 is lowered, causing processing precision to be lowered.